Dagvadorj's Blog
2019-09-29
Scrum guide
2012-09-13
Java annotations example
Annotations in Java is a very powerful enhancement that can save a lot of time for developers and programmers. Basically, it enables programmers to avoid creating bunch of configurations based on XML, database records, etc. Instead they can annotate certain classes or fields to achieve different configurations. That is how now we don't declare our servlets in web.xml with its class and URL pattern; instead we annotate them by typing @WebServlet in the Java file.
OK, the use case: Let's assume that we are developing a tax processing program. We have an entity class called Citizen.java which looks something like following:
Let's also assume that our program shall be a pretty generic one where we can define our processing formulas. Let's say we define formulas and set its variables to Citizen class' fields. Say we have if (A < (new Date()).getTime()) { B; } else { 0-B/2; }.
Obviously, some of the fields are irrelevant for formula designing. So, we define an annotation and annotate those fields which are relevant.
and
We have also defined an attribute called name for the annotation so that it can be more readable.
Finally, what and why are doing it is that we are building drop-down menus for setting variables in each formula we define. We are not able to fetch those fields annotated with @Calculated to fill those drop-down menus.
The ways to using these kind of functionality are left for your imaginations.
Of course, using reflections in run-time may make your program run slower. However, you can always cache the annotated fields list in your favorite embedded key-value store database.
2012-08-07
Embedded key-store store database wrapping-up
In my last post, I have mentioned about what a key-value store database and little about Sleepycat. While Sleepycat is great, it needs some configuration before actually using it. For this reason, I have written an wrapper which stores only unicode-based strings as key and value. The code is given in the following Gist. The usage example has been given in the comment.
2012-06-30
Embedded, persistent key-store
So here is the code chunk that did the trick! For a developer of modern languages like Python, it seemed like a lot of work for simple tasks. However, if you wrap it with your own code it can be helpful in many ways.
2012-04-27
2012-01-09
The Friendship of the Music: A review for Genghis Blues
- World at War timelines. http://www.schudak.de/timelines/tannutuva1911-1944.html retrieved Jan 03, 2012
- Friends of Tuva website. Frequently asked questions: http://www.fotuva.org/faq/part_1.html retrieved Jan 03, 2012
- A personal letter by Paul Pena in 1994. http://www.fotuva.org/gb/paul.html retrieved Jan 03, 2012
2011-03-21
Verilog ашиглан цуваа танигч хийсэн минь
Verilog хэрэглээд цуваа танигч хийснийгээ та бүхэнтэй хуваалцья гэж бодлоо. Электрон хэлхээ нь хир зай эзлэх вэ, хэлхээ их халах уу гэх мэт асуудлуудыг бодолцоогүйг анхаарна уу!
Энд цуваа танигчийгаа finite-state machine болон цуваа оролт, паралель гаралттай shift register ашиглан хийсэн юм.
Finite-state machine
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: fsm
// Tool versions: Xilinx ISE 12.1
// Description:
// Sequence detector using FSM
//
//////////////////////////////////////////////////////////////////////////////////
module fsm(clk, reset, inp, outp);
input clk;
input reset;
input inp;
output outp;
reg[2:0] state;
reg outp;
always @(posedge clk) // always trigger on clk
begin
if (reset) // check if reset
begin
state <= 3'b000; outp <= 1'b0; end else // else update outp begin if (state == 3'b111 & inp == 1'b0) outp <= 1'b1; else outp <= 1'b0; end case(state) // state transition 3'b000: if (inp == 1'b1) state <= 3'b001; else state <= 3'b000; 3'b001: if (inp == 1'b0) state <= 3'b010; else state <= 3'b000; 3'b010: if (inp == 1'b0) state <= 3'b011; else state <= 3'b000; 3'b011: if (inp == 1'b1) state <= 3'b100; else state <= 3'b000; 3'b100: if (inp == 1'b0) state <= 3'b101; else state <= 3'b000; 3'b101: if (inp == 1'b1) state <= 3'b110; else state <= 3'b000; 3'b110: if (inp == 1'b1) state <= 3'b111; else state <= 3'b000; 3'b111: state <= 3'b000; default: state <= 3'b000; endcase end endmodule
Хэлхээ нь ийм болж байна:
Shift-register
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: shr
// Tool versions: Xilinx ISE 12.1
// Description:
// Sequence detector using shift register
//
//////////////////////////////////////////////////////////////////////////////////
module shr(clk, reset, inp, outp);
input clk;
input reset;
input inp;
output outp;
reg[7:0] shr;
reg outp;
always @(posedge clk) // always trigger on clk
begin
if (reset) // check if reset
begin
shr <= 8'b00000000;
outp <= 1'b0;
end
else
begin
shr <= shr << 1;
shr[0] <= inp;
if (shr == 8'b10010110)
outp <= 1'b1;
else
outp <= 1'b0;
end
end
endmodule
За тэгээд 2уланг нь доорх тест модулиар ажиллууллаа даа:
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Module Name: shr_test
// Tool versions: Xilinx ISE 12.1
// Description:
// Verilog Test Fixture created by ISE for modules:
// shr
//
////////////////////////////////////////////////////////////////////////////////
module shr_test;
// Inputs
reg clk;
reg reset;
reg inp;
// Outputs
wire outp;
// Instantiate the Unit Under Test (UUT)
shr uut (
.clk(clk),
.reset(reset),
.inp(inp),
.outp(outp)
);
always #5 clk = ~clk;
initial begin
// Initialize
clk = 1;
inp = 0;
reset = 0;
// reset=1 when clk rises and reset=0
// in the next rise of clk
#9 reset = 1;
#3 reset = 0;
// Stimulus
#1 inp = 1;
#10 inp = 0;
#10 inp = 0;
#10 inp = 1;
#10 inp = 0;
#10 inp = 1;
#10 inp = 1;
#10 inp = 0;
#30
$finish;
end
endmodule
За тэгсэн чинь доорх симуляцууд гараад ирлээ.
Finite-state machine
Shift register